1. Field of the Invention
The invention relates to system bus architectures for electronic systems and in particular relates to an improved architecture for enhancing performance on system buses capable of supporting multiple master devices and multiple slave devices. More specifically, the invention relates to enhancing read performance on the read portion of the system bus by providing slave sideband signals for arbitration of multiple slave devices returning posted read requests from one or more master devices.
2. Discussion of Related Art
Electronic bus structures are generally utilized for interconnection of electronic circuits that exchanging information over the bus. In general, a master device is one that assumes temporary exclusive ownership of signal paths in the bus. Such temporary exclusive ownership permits the master device to communicate with another device on the bus typically referred to as a slave device. Arbitration logic circuits control distribution of temporary exclusive ownership to any of several master devices associate with the bus. Generally, a master device asserts a request signal to request temporary exclusive ownership of the bus. Arbitration logic associated with the bus detects bus request signals from master devices attached to the bus and determines which requesting master device should be granted the requested ownership. The arbitration logic then asserts a grant signal corresponding to the master device that is to receive ownership of the bus. The master device then performs desired transactions to exchange information with a desired slave device and relinquishes the temporary exclusive ownership.
In general, as presently practiced in the art, slave devices do not arbitrate for control of the bus. Rather, master devices assume control of the bus when granted temporary exclusive ownership by the arbitration logic. Slave devices merely respond to signals applied to the bus by a master device that has been granted ownership of the bus. Typically, the master device will issue a read request to a slave device to retrieve required data and write requests to transmit or store data. Write requests are often buffered or registered in the slave device so that the master device will relinquish control of the bus as soon as the required information is transferred to the slave device buffer. By contrast, as presently practiced in the art, read requests are generated by the master device and then await completion by the addressed slave device by return of the requested data.
As presently practiced in the art, some buses supporting multiple master devices and multiple slave devices do not permit posting of a plurality of read requests by one master device to a selected slave device. In particular, AMBA AHB buses do not permit a single master device to post multiple read requests to a single slave device. More specifically, the AMBA Specification Rev2.0 may be found on the World Wide Web at: http://www.armltd.co.uk. Rather, the AMBA AHB bus forces the master device to xe2x80x9cstallxe2x80x9d awaiting completion of a previous read request to that slave before permitting posting of additional read requests. In general, as presently practiced in the art, once a master device has generated a read transaction on the system bus, all further read transactions by that master device are delayed or stalled awaiting completion of the outstanding read request by that master device. The length of such a delay or stall is a function of the latency of the addressed slave devicexe2x80x94the delay required for the slave device to fetch the requested data and prepare it for application to the read portion of the system bus. This present architecture can inhibit optimal performance in a system when slave devices having different latencies.
As is evident from the above discussion, it would be desirable for a bus architecture to permit master devices to post read operations for a slave device for processing in parallel by that slave device. It is clear a need exists to permit improved system bus performance where slave devices exhibit latency.
The present invention solves the above and other problems, thereby advancing the state of the useful arts, by providing a bus architecture that permits a master device to post read requests to a slave device while enabling coordination of the return of data to the requesting master device. More specifically, the present invention provides for sideband signals enhancing the underlying bus architecture and associated with the slave devices whereby multiple slave devices processing posted read requests from multiple master devices arbitrate for control of the read portion of the system bus to return requested data to the requesting master devices.
In one exemplary preferred embodiment of the present invention, a system bus is provided that utilizes control signals similar to that of the AMBA AHB bus architecturexe2x80x94a high performance bus architecture useful for interconnecting processor, DMA and memory devices. Read requests are posted by master devices to corresponding slave devices. Sideband signals in accordance with the present invention provide for arbitrated control of the read portion of the bus by slave devices when each slave device has data ready for return to a corresponding master device. Other embodiments of the present invention provides for similar sideband signals to enhance other standard bus architectures providing the same benefit to enable multiple master devices to post reads to multiple slave devices.
A first aspect of the present invention provides for an electronic bus comprising: a master bus portion comprising signals used by a plurality of master devices to arbitrate for control of the master bus portion by one master device of the plurality of master devices and further comprising signals used by the plurality of master devices to initiate read and write bus transactions with a plurality of slave devices; a read bus portion comprising signals used by the plurality of master devices and by the plurality of slave devices for return of data requested by read transaction initiated by the plurality of master devices; and a slave bus portion comprising signals used by the plurality of slave devices to arbitrate for control of the read bus portion by one slave device of the plurality of slave devices.
Another aspect of the present invention further provides for a slave request signal path corresponding to each slave device of the plurality of slave devices; and a slave grant signal path corresponding to each slave device, wherein each slave device applies a signal to its corresponding slave request signal path to indicate readiness to return requested data corresponding to a previously posted read transaction, and wherein each slave device awaits receipt of a signal on the slave grant signal path granting the slave device temporary exclusive ownership of the read bus portion to permit application of the requested data to the read bus portion.